How to have a successful career
Imagine a workplace that you look forward to go to everyday - you hold the position you coveted for, enjoy the work and the benefits that come along with it, you are held in high esteem by your colleagues, have a say in the direction the organization is heading and pride on being very meticulous and effective in your work. Sounds too good to be true ?? Wrong !! You can and you should strive for it !!
In my opinion, too many folks short sell themselves or aim too low when it comes to work - they slip into their weekly routine, resist change and are quite content as long as their paycheck pays off their monthly expenses. At the other end of the spectrum, there are several professionals who are ambitious, hardworking and want to get ahead but have no clue how to do so.
This post initially began as a compilation of useful ideas from different sources to help me in my career goals and plans. I sincerely hope that this post will also help you in carving a niche for yourself in your career.
- The first step is to formulate a career plan - what your objectives are, what you would like to accomplish in the short term and long term and chalk out a plan to achieve these goals.
- Long term goals are important - We tend to overestimate what we can achieve in one month but largely underestimate what we can achieve in a year! Study the management structure in your organization and where you are placed currently. Analyze what you need to do to move to your desired position and any skills, knowledge that you need to acquire along the way.
- Short term goals include present deadlines, projects you are working on and actions that will benefit you and are in sync with your long term goals.
- Know your strengths and weaknesses - identify areas you excel in and have clear advantage over other colleagues. The clear way to do this is through feedback analysis - comparing the actual results from one of your decisions to the expected results. This feedback will be very valuable and you need to concentrate on your strengths.
- Know the difference between efficiency and effectiveness - efficiency is the art of doing things right while effectiveness is the art of doing the right things. Your boss will let you know how to do things right but it is upto you to figure out what’s the right job for you.
- Do NOT indulge in gossiping, tea break politics and other socializing in the workplace. Keep your eye on the job all the time, work hard to deliver high quality results - this is very important. Dont be complacent and always act one step ahead.
- Get your work noticed by your immediate superiors - one way to do this is to provide voluntary ideas or reports on how to improve design process, methodologies in the group. Always prepare well during presentations anticipating any problems/concerns that upper management may have and look at them as opportunities to cast a favorable impression.
- Three important words - “Act as if” Act as if you are the CEO of the organization, act as if you are running a team of individuals that you need to motivate to get the best out of them. That you are a junior does not matter, it’s the attitude that works wonders.
- Articulate and express yourself clearly during meetings, write well and be meticulous in documentation, records, reports etc. Be proactive and schedule performance reviews with your manager every three months for feedback and areas you can improve in.
- Dress well, groom yourself well and put on your best appearance. Too many folks neglect this but it counts.
- Plan your day ahead, split the work in tiny chunks of time and clock in the planned amount of time into that activity for best results. Sure, there will be emails/ phones ringing and colleagues dropping by for advice. A polite “later” from you and your colleagues will understand that you are in midst of something that is important to you.
- Always under promise and over deliver, this will also take care of any unexpected screwups and also aid in meeting deadlines you have committed to.
- Develop the right attitude, have a nice smile, be positive and cheerful and take pride on what you do. If you dont have anything nice to say, clam up. If some colleague moans about his/her job, be sympathetic and nod discerningly. Do not offer anything make more than that.
- Know your values and the organization values and check if they are compatible. If they are not, it is highly unlikely that you will enjoy your work. Never lie, do not take sides, stand up for your colleagues and develop team spirit. In times of need, your colleagues will stick to you if you follow these rules.
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Serial to Parallel and Parallel to Serial conversion
Serial to Parallel conversion is common in designs where the clock runs at slower frequency than the incoming serial stream. To maintain the throughput, the serial data is converted to parallel data. Similarly, high speed parallel data can be converted to serial stream before output from a chip - as it is very hard to manage skew between different data lines.
We will look at verilog
CODE:
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module serial_to_parallel ( parallel_out, serial_in, shift_enable, clock, reset_n);
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parameter SIZE = 4;
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output [SIZE-1] parallel_out;
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input serial_in;
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input shift_enable;
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input clock;
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input reset_n;
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reg [SIZE-1] parallel_out;
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always @(posedge clock or negedge reset_n) begin
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if (~reset_n)
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parallel_out <= 0;
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else if (shift_enable)
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parallel_out <= {serial_in, parallel_out[SIZE-1:1]};
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end
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endmodule
CODE:
Sphere: Related Content-
module parallel_2_serial (serial_out, parallel_in, load_enable,shift_enable, clock, reset_n);
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parameter SIZE=5;
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output serial_out;
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input clock;
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input reset_n;
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input load_enable;
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input shift_enable;
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input [SIZE-1:0] parallel_in;
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reg [SIZE-1:0] parallel_r;
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always @(posedge clock or negedge reset_n) begin
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if (~reset_n)
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parallel_r <= 0;
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else if (load_enable)
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parallel_r <= parallel_in;
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else if (shift_enable)
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parallel_r <= {1'b0, parallel_r[SIZE-1:1]};
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end
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assign serial_out = parallel_r[0];
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endmodule
RTL coding guidelines - Doing it right the first time!
- Document in detail interface timing and signal descriptions, clock and reset strategy, modular view of the design and FSMs prior to RTL coding.
- Have a comment "header" for each module with functionality description, version and a log of past changes. This can be managed using a revision control system like CVS.
- Do not include more than one module in one file and the module name should match the filename in the design.
- Be generous while adding comments where necessary - like inputs and outputs.
- Indent your code and use Emacs verilog
- Split the design into separate modules based on clock domains.
- Use separate always @ blocks for sequential and combinational logic. Always use non-blocking assignments for sequential logic and blocking assignments for combinational logic.
- Avoid "parallel_case full_case" compiler directives and always add a default clause for case statements.
- Do NOT assign the same variable in more than one always@ block.
- Use "if-else" only for priority encoders and case statements for parallel states.
- Avoid inferring latches in the design, clock gating and instantiating gates in the design to keep it technology independent.
- Register all inputs and outputs in the design to ease timing closure.
- Use dual stage synchronizer cells available in the library than two stage flops for synchronization.
- Use reset synchronizers for asynchronous resets. Add DFT bypass muxes for reset and clock controllability where necessary.
- Avoid combinational loops in the design to aid timing analysis and DFT
- Avoid using clock as data for flop inputs for hassle free DFT insertion.
- Do not mix posedge and negedge flops in the same module where possible.
- Always separate the combinational and sequential logic in a FSM with two always@ blocks.
- Always code with design reuse in mind - For example, FIFOs can be made generic and can be customized by passing parameters while being instantiated.
- Remember the thumb rule - Be conservative in what you transmit and be generous in what you receive
- Parenthesize all operations without depending on the reader to figure out the precedence of operators.
- Add assertions where necessary to aid verification
- Lint your design for syntax/sematic checks and clock-reset policies.