Gray code counters
While designing modules with asynchronous clock transfers, one may encounter the problem of transferring multi-bit data bus from one clock domain to another. To dual synchronize these bits and hope that all the bits are latched on the same clock is problematic. To eliminate this problem, we use Gray code counters where only one bit changes during each clock transition.
The most common Gray code is where the lower half of the sequence is exactly the mirror image of first half with only the MSB inverted. We illustrate the 3-bit binary Gray code as an example.
Gray code counter schematic (from Cliff Cumming's paper)
Gray code to equivalent binary conversion is simple and is as shown below
bin[2] = gray[2];
bin[1] = gray[2] ^ gray[1] (XOR function)
bin[0] = gray[2] ^ gray[1] ^ gray[0]
Verilog
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module gray2binary_converter (binary, gray);
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parameter NUM_BITS = 3;
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output [NUM_BITS-1:0] binary;
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input [NUM_BITS-1:0] gray;
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reg [NUM_BITS-1:0] binary;
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integer i;
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always @(gray) begin
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for (i=0; i<NUM_BITS; i=i+1)
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binary[i] = ^(gray>> i); // Add padded 0's for the significant bits
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end
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endmodule
Similarly, the Binary to Gray conversion is achieved by
gray[2] = binary[3];
gray[1] = binary[2] ^ binary[1];
gray[0] = binary[0] ^ binary[1];
Verilog code is
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module binary2gray_converter (gray, binary);
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parameter NUM_BITS = 3;
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output [NUM_BITS-1:0] gray;
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input [NUM_BITS-1:0] binary;
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assign gray = (binary>> 1) ^ binary; // Right shift binary vector and XOR
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endmodule
The gray code counter can be implemented using these functions - please refer to Cliff Cumming's excellent paper on asynchronous clock domains.
Sphere: Related ContentAsynchronous and Synchronous Resets
Designing power-up reset sequence and reset structures in a chip is a critical task and there are many issues one needs to be aware of. Incorrect reset generation can cause intermittent failures that are hard to debug and in some cases can also make a chip DOA (Dead on Arrival).
In this post, we will look at asynchronous/synchronous resets, reset synchronizers and also factors that may affect reset sequence in a chip. Most of the information presented here is derived from Cliff Cummings et. al. excellent paper and the reader is strongly recommended to read the paper at his leisure.
Resets can be either synchronous or asynchronous and each flip-flop has a timing window during which the reset cannot change transition. Recovery time is known as the minimum time the reset should be stable BEFORE the active clock edge (setup time) while Removal is the minimum time the reset should be stable AFTER the active clock edge (hold time).
Advantages of using Synchronous resets are :
- The reset is active only on active clock edge.
- Fewer number of gates (although negligible)
- Timing analysis is easier as the reset is synchronous to the clock.
A major disadvantage of synchronous reset design is that the clock should be running at the time of reset. In some chips, this may not be feasible due to gated clocks or due to requirements of the design.
Advantages of using Asynchronous resets are :
- No extra logic on the datapath making timing closure easier
- No clock required at the time of reset
The problem with asynchronous resets is that they can cause flops to go metastable, hence care must be taken at the time of assertion or deassertion of reset. Another issue is that timing analysis should include checks for recovery and removal times.
Reset Synchronizer
A novel technique to overcome the issues with asynchronous resets is to use Reset synchronizers. A reset synchronizer ensures that the reset removal does not cause any metastable problems – it resets the design asynchronously ( i.e. without a running clock) while the deassertion is synchronous!
Reset synchronizer
A reset synchronizer circuit is shown above, the two flops are dual stage synchronizers to synchronize the reset to the clock. On assertion of the chip reset, the synchronizer output drives the internal reset to the flops in the design. Deassertion can only happen during the next active edge. An important point to note is that the second flop in the synchronizer cannot go metastable as both the input and output points are both low when the reset is removed.
The two flops in the reset synchronizer should not be made scannable for DFT and a bypass mux is added at the output of the reset synchronizer to control the reset in test modes. Also note that a separate reset synchronizer will be required for each clock domain.
Another important requirement in many multi-clock domains is sequencing of resets – i.e. reset in one clock domain must be deasserted prior to reset in another clock domain. The author has come across designs where this requirement was neglected or overlooked causing critical issues in Silicon. A circuit below using reset synchronizers illustrates this.
Reset Sequencer (resetb is deasserted only later than reseta)
Sphere: Related Content
Clock Dividers
Clock dividers are common in ASIC
Divide-by-two clock
A divide-by-two clock that is synchronous to the clock source is used very widely. The figure below shows a simple divide-by-2 circuit and the corresponding waves.
Divide-by-2 Circuit with 50% duty cycle
Divide-by-3 clock with 33/66 duty cycle
A divide-by-3 clock can be generated from a clock source as shown in the figure below. Note that the source clock has a 50% duty cycle while the divide-by-three output does not.
Divide-by-3 clock with 33/66 duty cycle
Divide-by-3 clock with 50% duty cycle
The above circuit can be modified to generate a divide-by-3 clock with 50% duty cycle. This requires clock gating and should be avoided as it can generate glitches in the design. The first flipflop in the circuit generates the high transition while the second flipflop generates the low transition when the clock goes low to give a 50% duty cycle.
Divide by 3 clock with 50% duty cycle
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