Serial to Parallel and Parallel to Serial conversion
Serial to Parallel conversion is common in designs where the clock runs at slower frequency than the incoming serial stream. To maintain the throughput, the serial data is converted to parallel data. Similarly, high speed parallel data can be converted to serial stream before output from a chip - as it is very hard to manage skew between different data lines.
We will look at verilog
CODE:
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module serial_to_parallel ( parallel_out, serial_in, shift_enable, clock, reset_n);
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parameter SIZE = 4;
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output [SIZE-1] parallel_out;
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input serial_in;
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input shift_enable;
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input clock;
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input reset_n;
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reg [SIZE-1] parallel_out;
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always @(posedge clock or negedge reset_n) begin
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if (~reset_n)
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parallel_out <= 0;
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else if (shift_enable)
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parallel_out <= {serial_in, parallel_out[SIZE-1:1]};
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end
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endmodule
CODE:
Sphere: Related Content-
module parallel_2_serial (serial_out, parallel_in, load_enable,shift_enable, clock, reset_n);
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parameter SIZE=5;
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output serial_out;
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input clock;
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input reset_n;
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input load_enable;
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input shift_enable;
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input [SIZE-1:0] parallel_in;
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reg [SIZE-1:0] parallel_r;
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always @(posedge clock or negedge reset_n) begin
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if (~reset_n)
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parallel_r <= 0;
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else if (load_enable)
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parallel_r <= parallel_in;
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else if (shift_enable)
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parallel_r <= {1'b0, parallel_r[SIZE-1:1]};
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end
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assign serial_out = parallel_r[0];
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endmodule