THE VLSI HOMEPAGE

Traditional scan based designs employ either Muxed-scan technique or Level Sensitive Scan Design (LSSD) techniques to achieve test coverage. In scan based designs, the registers are hooked up to form serial shift register chains - this aids in capturing all the combinational logic faults between two pipelined registers.

There is a shift phase during which the ATE pattern is shifted serially through the scan chain from the IO pins. Once the ATE pattern is shifted through the scan chain, there is a capture phase that allows the flops in the scan chain to capture the combinational logic output at their input pins. Following this capture phase, the pattern is shifted out serially and compared with the expected vector from ATPG.

Each clock domain can have it’s flops stitched into a single/multiple scan chains, based on the number of flops in the clock domain - stitching multiple scan chains is an advantage as it reduces tester time since we can parallely load all the scan chains. Usually mixing clock domains or posedge and negedge flops in a scan chain is not recommended as it can cause timing issues. Use of lock-up latches is advised if crossing from posedge to negedge flops in a scan chain.

Advantages of scan based design are several - high fault coverage with moderate increase in logic, the entire insertion is automated. The main disadvantage of scan based testing is that it runs at low speed typically 50 MHz - this is very slow for high speed designs and where at-speed testing is critical.

Muxed scan

The figure below shows a muxed-scan flop and associated waveform - the D pin is the normal functional input, SI is the scan input and SE is the scan enable to shift in and shift out data out of the flop. The Q output of the flop is connected to SI pin of the next flop in the scan chain. During the capture phase, the Q latches the D input and the data is shifted out.

Muxed scan flip-flop

LSSD scan

A schematic of LSSD scan flop and waves is shown in the figure below. The relationship between clocks is also shown - the SCK1 and SCK2 are active during shift phase while the CLK is active during the capture phase.

LSSD scan flop

Differences between Muxed scan and LSSD are several - in muxed scan, the data and test paths are the same i.e. the test path is muxed with the functional path and can add additional logic on the functional path making timing closure harder. Muxed scan flops are smaller in area and are faster but the same functional clock is used for shift/capture and can cause shift violations. In contrast, the LSSD scan paths are different from functional paths, have two different non-overlapping clocks for shifting data in and out and one capture clock. LSSD flops are larger in size but the timing closure is easier as we never run into shift violations.

Main disadvantage of scan based testing is that it runs at low speed typically 50 MHz - this is very slow for high speed designs and where at-speed testing is critical.

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