Gray code counters
While designing modules with asynchronous clock transfers, one may encounter the problem of transferring multi-bit data bus from one clock domain to another. To dual synchronize these bits and hope that all the bits are latched on the same clock is problematic. To eliminate this problem, we use Gray code counters where only one bit changes during each clock transition.
The most common Gray code is where the lower half of the sequence is exactly the mirror image of first half with only the MSB inverted. We illustrate the 3-bit binary Gray code as an example.
Gray code counter schematic (from Cliff Cumming's paper)
Gray code to equivalent binary conversion is simple and is as shown below
bin[2] = gray[2];
bin[1] = gray[2] ^ gray[1] (XOR function)
bin[0] = gray[2] ^ gray[1] ^ gray[0]
Verilog
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module gray2binary_converter (binary, gray);
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parameter NUM_BITS = 3;
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output [NUM_BITS-1:0] binary;
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input [NUM_BITS-1:0] gray;
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reg [NUM_BITS-1:0] binary;
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integer i;
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always @(gray) begin
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for (i=0; i<NUM_BITS; i=i+1)
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binary[i] = ^(gray>> i); // Add padded 0's for the significant bits
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end
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endmodule
Similarly, the Binary to Gray conversion is achieved by
gray[2] = binary[3];
gray[1] = binary[2] ^ binary[1];
gray[0] = binary[0] ^ binary[1];
Verilog code is
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module binary2gray_converter (gray, binary);
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parameter NUM_BITS = 3;
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output [NUM_BITS-1:0] gray;
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input [NUM_BITS-1:0] binary;
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assign gray = (binary>> 1) ^ binary; // Right shift binary vector and XOR
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endmodule
The gray code counter can be implemented using these functions - please refer to Cliff Cumming's excellent paper on asynchronous clock domains.
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