Edge Detector
Let's start with the most fundamental design that is widely used in logic design - the edge detector. The edge detector generates a synchronous one clock cycle pulse upon a change in level (transition) of a signal from high->low or low->high. Edge detectors are used to detect the initial condition and to trigger other logic dependent on this signal - an example would be an active low interrupt where the transition from high to low indicates an interrupt has been asserted.
The edge detect circuit and waves are depicted in the thumbnail below - this detects both rising and falling transitions of the signal.
Edge Detector Circuit
We will now look at the verilog
CODE:
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always @(posedge CLK or negedge RST_L) begin
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if (~RST_L) begin
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IN_D1 <= 1'b0;
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IN_D2 <= 1'b0;
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end
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else begin
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IN_D1 <= IN;
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IN_D2 <= IN_D1;
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end
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end
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wire OUT = IN_D1 ^ IN_D2; // detects both rising edge and falling edge transitions
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wire OUT_posedge = IN_D1 & ~IN_D2; // detects rising edge
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wire OUT_negedge = ~IN_D1 & IN_D2; // detects falling edge
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